An associative memory system called Content Addressable Memory (CAM) has been developed to permit its memory cells to be referenced by their contents. Thus CAM has found use in lookup table implementations such as cache memory subsystems and is now rapidly finding use in networking system applications such as network address translation, pattern recognition, and data compression. CAM's most valuable feature is its ability to perform a search and compare of multiple locations as a single operation, in which search data is compared with data stored within the CAM. Typically search data is loaded onto search lines and compared with stored words in the CAM. During a search-and-compare operation, a match or mismatch signal associated with each stored word is generated on a matchline, indicating whether the search word matches a stored word or not.
A CAM stores data in a matrix of cells, which are generally either SRAM based cells or DRAM based cells. Until recently, SRAM based CAM cells have been most common because of their relatively simpler implementation than DRAM based CAM cells. However, to provide ternary state CAMs, i.e., where each CAM cell can store one of three values: a logic “0”, “1” or “don't care” result, ternary SRAM based cells typically require many more transistors than ternary DRAM based cells. As a result, ternary SRAM based cells have a much lower packing density than ternary DRAM based cells.
A typical DRAM based CAM block diagram is shown in FIG. 1. The CAM 10 includes a matrix, or array 25, of DRAM based CAM cells (not shown) arranged in rows and columns. A predetermined number of CAM cells in a row store a word of data. An address decoder 17 is used to select any row within the CAM array 25 to allow data to be written into or read out of the selected row. Data access circuitry such as bitlines and column selection devices, are located within the array 25 to transfer data into and out of the array 25. Located within CAM array 25 for each row of CAM cells are matchline sense circuits, which are not shown, and are used during search-and-compare operations for outputting a result indicating a successful or unsuccessful match of a search word against the stored word in the row. The results for all rows are processed by the priority encoder 22 to output the address (Match Address) corresponding to the location of a matched word. The match address is stored in match address registers 18 before being output by the match address output block 19. Data is written into array 25 through the data I/O block 11 and the various data registers 15. Data is read out from the array 25 through the data output register 23 and the data I/O block 11. Other components of the CAM include the control circuit block 12, the flag logic block 13, the voltage supply generation block 14, various control and address registers 16, refresh counter 20 and JTAG block 21.
The extensive use of CAM's in current applications inevitably results in a demand for higher density and higher speed CAM chips that consume minimal power. Unfortunately, higher density arrays and operating speeds are realized primarily at the expense of power. Although advanced semiconductor processes continue to shrink device geometries and reduce dynamic power dissipation, overall power consumption remains substantially constant due to increased leakage power. Hence, circuit techniques have been proposed in the prior art to reduce power consumption of CAM devices.
One technique for reducing matchline power consumption is to precharge all matchlines to a miss voltage level, such as ground, and self-time activation of matchline sense amplifiers using a reference matchline row hard wired to a hit, or match condition. This technique is disclosed in detail in commonly owned U.S. patent application Ser. No. 10/258,580 having publication number US20030161194A1. FIG. 2 is a general circuit schematic of a portion of a CAM array that can be used in array 25 of FIG. 1 to illustrate the operation of the precharge-to-miss matchline sensing scheme.
CAM array 25 is subdivided into the memory array portion 30 and matchline sense circuit portion 32. Only the two last logical rows of the memory array portion 30 and matchline sense circuit portion 32 is shown, and wordlines WL are intentionally omitted to simplify the schematic of FIG. 2. But it will be understood by those skilled in the art that typically, wordlines would run in parallel to the matchlines and each wordline would connect to all cells in that particular row. For ease of illustration, matchline sense circuit portion 32 has been split in to two sections at either side of memory array portion 30. The memory array portion 30 includes CAM cells 34, reference CAM cells 36, bitlines BLj, complementary bitlines BLj*, searchlines SLj, complementary searchlines SLj*, matchlines MLi, and reference matchline RML. CAM cells 34 and 36 are arranged in rows and columns, and can be any well known type of cell such as a DRAM or SRAM based CAM cell configured for binary or ternary data storage. CAM cells 34 of a row are connected to a common matchline MLi, and CAM cells 34 of a column are connected to a common pair of search lines SLj/SLj* and a common pair of bitlines BLj/BLj*, where i is an integer value between 0 and n, and j is an integer value between 0 and m. The bottom row of array 25 is a reference matchline row 38, having reference elements constructed and arranged identically to the elements of the regular row above it. Reference CAM cells 36 are connected to RML and are configured such that they never form a conduction path between RML and ground, and therefore will not affect the outcome of a compare operation.
Each sense circuit of matchline sense circuit portion 32 includes a current source 40, a comparator circuit 42, and n-channel precharge transistors 44. Current source 40 connected to VDD applies current to its respective matchline MLi in response to feedback control signal EN*, for raising the voltage potential of the matchline MLi. Precharge transistors 44 couple each matchline MLi to ground in response to a precharge signal PRE received at their gates. Matchlines MLi are connected to their respective comparator circuits 42, where each comparator circuit 42 generates a signal ML_OUTi. The output of NOR gate 46 is inverted by inverter 48 to generate active low enable signal EN*, which is received by all current sources 40. The sense circuit for the reference row 38 is identical to the sense circuit described above, however, signal RML_OUT from comparator 42 of reference row 38 is connected to one input of NOR gate 46, while the other input of NOR gate 46 is connected to precharge signal PRE.
In operation, the matchline sense circuit portion 32 is self-timed to reduce power consumption of the CAM chip through the feedback loop of RML_OUT, NOR gate 46, inverter 48 and current sources 40. After a matchline MLi is precharged to ground by precharge transistors 44, a search word is asserted on the searchlines SLj, and the current source 40 on matchline MLi turns on. If any cell 34 on the matchline MLi is in a mismatch condition, MLi is coupled to ground and comparator 42 generates a low logic level output. If all cells of a word are in a match condition, there will be no conduction path from MLi to ground, allowing a voltage potential to develop and be sensed by comparator 42 to generate a high logic level output. Reference matchline RML has reference cells 36 in which internal storage nodes are hardwired to a match condition, such that there can never be a current path between RML and ground, therefore always providing a match condition. The reference matchline sense circuit detects when the RML potential exceeds a certain predetermined voltage level, called the sense voltage threshold, in order to disable all the other current sources. In this way, each matchline MLi receives just enough current to detect a match condition, but no more, saving substantial power. Therefore, matchline power is saved since all matchlines are precharged to ground and the current sources are self-timed to turn off and stop applying current to the matchlines.
Currently, commercial CAMs are limited to 18 Mb of storage and 100 million searches per second on a 144-bit search word, at typically 5 Watts per CAM chip. Compared to the conventional memories of similar size, CAMs consume considerably larger power. This is partly due to the fully-parallel nature of the search operation, in which a search word is compared in parallel against every stored word in the entire CAM array. Statistically, since a CAM will have many more miss-matches than matches during search operations, there is a large amount of power wasted in the array in each search cycle. Furthermore, while it is desirable to reduce power consumption in the memory array during search operations, the performance or speed at which match results are provided should not be adversely impacted.
It is, therefore, desirable to provide a matchline sensing scheme that can reduce power consumption of the memory array while maintaining or improving matchline sensing performance.